GitHub

High-Performance-8-Bit-Comparator-Using-Pipeline-And-Clock-Gating-Technique.

This project presents a High-Speed Pipelined 8-bit Comparator implemented using 90nm CMOS technology. The design achieves optimized timing, low power, and clean DRC/Connectivity verification results.
GitHub

SystemVerilog Verification: 8-bit Digital Comparator

This repository contains a complete SystemVerilog verification environment for a parameterizable Digital Comparator. The project demonstrates a layered testbench architecture (similar to UVM phases) ...
IEEE

Implementation of 8-bit Digital Comparator with Low Power and Low Area for High-Speed Applications

Abstract: This research introduces a highly efficient digital comparator designed to handle 8-bit comparisons, with a primary focus on achieving minimal area usage, maximum speed, and low power ...
IEEE

Pioneering 8-bit Comparator Architecture with Independent (INDEP) Gate Control

Abstract: This paper presents a novel 8-bit comparator architecture designed using the Independent Gate Control (INDEP) technique to enhance speed and energy efficiency. The proposed design integrates ...