EDN

DDR4 Design Considerations

DDR4 represents a substantial upgrade to JEDEC’s dynamic random access memory (DRAM) standard, with numerous changes designed to lower power consumption while delivering higher density and bandwidth ...
EDN

LeCroy Announces the Industry’s First DDR4 Bus and Timing Analyzer

DDR4 is the next evolution of the double data rate memory technology currently under development by the JEDEC standards organization. With operating frequencies from 800 Mhz to 1600 Mhz, DDR4 ...
Electronic Design

LeCroy Announces DDR4 Bus and Timing Analyzer

February 1, 2012. LeCroy Corp. has announced a new validation platform that provides DDR4 bus and JEDEC timing analysis. Based on LeCroy’s first-generation DDR3 analyzer, the new Kibra 480 platform ...
IEEE

Timing margin analysis and Power measurement with DDR4 memory

Abstract: DIMMs built with DDR4 (Double Data Rate 4th-generation) SDRAM (Synchronous Dynamic Random-Access Memory) are the current memory components used on HPC (High Performance Computing) systems.
Electronic Design

Functional Testing and Validation for DDR4 and LPDDR4

Representing the most recent generation of double-data-rate (DDR) SDRAM memory, DDR4 and low-power LPDDR4 together provide improvements in speed, density, and power over DDR3. However, such speed and ...